MPC8641/D Integrated Host Processor Class July 7 - July 11, 2008 in San Jose, CA PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING
Description:	This is a 5-day class covering hardware and software aspects of the MPC8641/D Integrated Host Processor. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded Power Architecture Core (e600 with MMU and Caches), Local Bus Controller, PCI Express, Serial RapidIO, new Enhanced Three Speed Ethernet Controllers, DMA controller, DDR2 Controller, Reset and configuration and Multiprocessor Interrupt Controller.
Objectives:	Learn the architecture of e600 core Configure MMU and set up caches (L1 and L2) Learn the exception processing in e600 Configure the multiprocessor interrupt controller Configure Local bus memory controller Configure the DDR2 controller Configure and use PCI Express Configure and use Serial RapidIO bus interface Reset and hardware configuration of the MPC8641/D Configure and use the Enhanced Three Speed Ethernet Controller
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is useful.
Date:	Monday, July 7 to Friday, July 11, 2008
Time:	8:30am to 5:00pm
Location:	Freescale Semiconductor Sales Office 5300 Stevens Creek Blvd Suite 550 San Jose, CA 95129 MAP ... HOTELS
Fee:	US $1950.00 for the 5-day course. This fee includes the course handouts and manuals. Payment should be arranged no later than one week prior to the start of class.
Terms:	Arnewsh Inc. recommends early registration to ensure availability prior to classes filling up. Cancellation must be made no later than one week prior to the start date. Otherwise the student will be charged for the class. Substitutions from the same company is allowed. In the event of insufficient enrollment, Arnewsh Inc. reserves the right to cancel the class with at least 1 week advance notice.
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