MSC8101 Digital Signal Processor

 Dates Offered:
NO OPEN CLASSES ARE PLANNED AT THIS TIME,
PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING

Description: This is a 5-day class covering the hardware and software aspects of the MSC8101 digital signal processor. This class consists of lecture, and exercises.

Learn to design systems based on MSC8101 and write programs for various chip sub-modules. This includes the DSP Core, the RISC communication processor module (CPM) and its various serial channels, the enhanced filter coprocessor (EFCOP), DMA, and the system integration unit.

Objectives:
  • Overview of the SC140 Core
  • Enhanced Filter Coprocessor (EFCOP)
  • DMA Engine
  • Internal Memory and Buses (QBus and 60x System Bus)
  • Reset, Initial Configuration and Clock requirements
  • Memory Controllers (UPM, SDRAM, and the general purpose)
  • Interrupt Controllers and exception handling
  • Communication Processor Module (CPM)
  • Fast Communication Channels with ATM, HDLC, and Ethernet protocols
  • Serial Communication Channels with UART, HDLC, and Ethernet protocols
  • Multichannel Communication Channels with HDLC and Transparent protocols
  • Serial Interface (SI) with Time Slot Assigners (TSA)
  • Other optional topics are SMC, SPI, I2C, and Timers
Prerequisites: This course covers a short overview of the SC140 Core DSP processor. If detailed understanding of the core is needed, the attendees should take the SC140 class as well.

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