MPC8572 PowerQUICC III Microcontroller Class Dates Offered: August 25 - August 29, 2008 in Austin, TX September 15 - September 19, 2008 in Woburn, MA (Boston Area) September 22 - September 26, 2008 in San Jose, CA PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING
Description:	This is a 5-day class covering hardware and software aspects of the MPC8572 PowerQUICC III microcontrollers. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded dual Power Architecture Cores (e500v2 with MMU and Caches), Enhanced Local bus, PCI Express, Serial RapidIO, new Enhanced Three Speed Ethernet Controllers, DMA controllers, DDRII/III Controller, Table Lookup Units, Pattern Matching Engine, Reset and configuration and Interrupt Controller.
Objectives:	Learn the architecture of e500v2 core Configure MMU and set up caches (L1 and L2) Learn the exception processing in e500v2 Configure the interrupt controller Configure Enhanced Local bus memory controller Configure the DDRII/III controller Configure and use the Enhanced Three Speed Ethernet Controller Configure and use PCI Express Configure and use Serial RapidIO bus interface Reset and hardware configuration of the MPC8572 Configure and use Table Lookup Units Overview of Pattern Matching Engine
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is recommended. On-site classes can be customized to exclude topics which are not of interest.
back to	TechnicalTraining