P40x0 QorIQTM Multicore Communication Processor Class Dates Offered: September 13 to September 17, 2010 in San Jose, CA PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING THIS CLASS IS AVAILABLE TO THOSE HAVING NDA WITH FREESCALE SEMICONDUCTOR FOR P40x0
Description:	This is a 5-day class covering hardware and software aspects of the QoreIQ P4080 Multicore Communication Processor. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded Power Architecture Cores (e500mc with MMU and Caches), Buffer Manger, Queue Manager, PAMU, Frame Manager (icluding Parser, KeyGen, Coarse Classifier, Policer, and the MAC units), PCI Express, Serial RapidIO, DMA controllers, Enhanced Local bus, DDRII/III Controller, Reset and configuration and Interrupt Controller.
Objectives:	Learn the architecture of e500mc core Configure MMU and set up caches (L1, L2, and L3) Learn the exception processing in e500mc Configure the interrupt controller Reset and hardware configuration of the P4080 Configure Peripheral Access Management Unit (PAMU) Configure and use Buffer Manager (BMan) Configure and use Queue Manager (QMan) Configure and use Frame Manager (FMan), Parser, KeyGen, Coarse Classifier, and Policer Configure and use the MAC units (dTSEC and 10GEC) Configure and use DMA Controllers Configure and use PCI Express Configure and use Serial RapidIO Configure Enhanced Local bus memory controller Configure the DDRII/III controller
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is recommended. On-site classes can be customized to exclude topics which are not of interest.
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