QorIQTM P20x0 Integrated Processors Class Dates Offered: August 23 to August 27, 2010 in San Jose, CA PLEASE CONTACT ARNEWSH INC. FOR ONSITE TRAINING THIS CLASS IS AVAILABLE TO THOSE HAVING NDA WITH FREESCALE SEMICONDUCTOR FOR P20x0
Description:	This is a 5-day class covering hardware and software aspects of the QorIQ P2020/P2010 Integrated Processors. A customized, shorter version can be arranged for on-site training. Students will learn to design and write programs for various chip sub-modules. This includes the embedded dual Power Architecture Cores (e500v2 with MMU and Caches), Enhanced Local bus, PCI Express, Serial RapidIO, new Enhanced Three Speed Ethernet Controllers, DMA controllers, DDRII/III Controller, Reset and configuration and Interrupt Controller.
Objectives:	Learn the architecture of e500v2 core Configure MMU and set up caches (L1 and L2) Learn the exception processing in e500v2 Configure the interrupt controller Configure Enhanced Local bus memory controller Configure the DDRII/III controller Configure and use the Enhanced Three Speed Ethernet Controller Configure and use PCI Express Configure and use Serial RapidIO Configure and use DMA controllers Reset and hardware configuration of the P2020/P2010
Prerequisites:	To benefit most from the course, familiarity with the Power Architecture is recommended. On-site classes can be customized to exclude topics which are not of interest.
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